The escalating demands for high density and performance associated with non-volatile memory devices require small design features, high reliability and increased manufacturing throughput. The reduction of design features, however, challenges the limitations of conventional methodology. For example, the reduction of design features makes it difficult for the memory device to meet its expected data retention requirement.
In addition, once a memory device, such as an electrically erasable programmable read only memory (EEPROM) device, has been fabricated, the memory device must be able to be programmed and erased in an efficient manner. In flash EEPROM devices, an entire sector of memory cells may be programmed or erased together. As the product density (e.g., the density of the core memory cell array) increases, it is difficult to increase programming speeds without increasing the programming voltages/power applied to the memory cells. It is also difficult to maintain fast programming speeds at lower power levels. Increasing programming voltages/power, however, often creates problems associated with the memory devices. For example, increasing programming voltages may lead to breakdowns in various layers, such as dielectric layers, used in the memory device. These problems may make it difficult to program and/or erase the memory device in an efficient manner and, ultimately, may lead to device failure.